Services

1. ASIC Design

   • RTL design for ASIC and FPGA

RTL - MIPI CSI-2, CPHY, DPHY, Glue Logic, Reed Solomon Forward Error Correction, Signal Processing, Analog Circuit Calibration

1. • Analog circuit modeling

Modeling of ADCs/DACs/general analog circuits in SystemVerilog real datatype or integer datatype. Verilog-A/Wreal models for simple circuits.

1. • Matlab

   • C/C++ Modeling of digital blocks

   • High Level Synthesis of algorithms in C to Verilog

Completed AMD Xilinx Vivado HLS models for moving average and longest common subsequence problems

1. • Constrained Random Verification of Small IPs (without UVM)

Verification of small IPs without the overhead of full blown UVM, but extracting maximum coverage from a minimalist testbench

1. • DFT

Insertion of compressed scan chain during synthesis (Cadence Genus)

ATPG pattern generation for the synthesized design

Gate level simulation of ATPG patterns

1. • Synthesis

   • Physical Design

Numerous projects completed in nodes from 20nm to 130nm covering up to a few million instances.

Mixed signal chips, small teams no problem!

1. • LVS, DRC

Closing LVS/DRC for mixed signal chips

1. • Automation

Stitching flows with python/PERL/TCL/Make scripts, automation with scripts

2. FPGA design

   • RTL design for FPGA target

3. Bioinformatics

   • ASIC/FPGA design for bioinformatics

   • HLS for bioinformatics algorithms

   • C/C++ developement for bioinformatics algorithms

4. Resources for Customer Support

   • Creating application notes, utilities to help customer derive chip configuration parameters