Products

Ehgu: An opensource Design Library distributed as DWYW (Do Whatever You Want)

• Building blocks like FIFO, Clock Mux, Fractional/Integer Clock Divider, SECDED, Hamming code, etc..

Thee: An opensource Verification Components library (DWYW)

• Pre-UVM verification components like clock generator - with/without jitter model

• Analog models in SystemVerilog

  • CDR, Fractional/Integer PLL, ADC - Flash, SAR, Delta Sigma, Pipelined, DAC - R String, R-2R Ladder

Utilities (DWYW)

• Scripts for frequently used tasks in TCL/Python

Education

• Design, Verification and Utilities are well documented in

https://www.amazon.com/Ehgu-Proposal-efficient-design-ecosystem-ebook/dp/B07TZGPKC8

Open Source older version here

https://github.com/3vm/dsn_verif/blob/master/Ehgu_proposal_full.pdf