Survey of Chisel Hardware Construction Language

2022 Nov 25

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Introduction

The chip design process has been getting more and more productive by providing intuitive constructs for commonly recurring design patterns. You could say that this process has been happening as early as when the symbol of a transistor with W/L parameters replaced the layout of a transistor in the schematic capture based design process. Further evolution created Hardware Description Languages (HDL) like Verilog and VHDL. The SystemVerilog (SV) HDL is the most mature output of this phenomenon. Or is it?

A careful look at the HDL landscape in the year 2022 reveals an underdog - Constructing Hardware in a Scala Embedded Language, Chisel for short. The name is very attractive and conjures up an image of an IC designer wielding a chisel in hand to carve ICs out of raw silicon! Indeed, Chisel does provide many attractive features that takes the design abstraction a level above SV.

This blog is about how Chisel compares to the incumbent SV based on this Chisel book -

https://www.imm.dtu.dk/~masca/chisel-book.html

Chisel Highlights

Natively object oriented.

Large Scala code base available for extension.

Higher level of abstraction was planned from the start, primarily by not bothering with clocks and resets in every piece of code.

Excels in describing algorithms, expression of logic and processor cores.

A window into current and future opensource designs - Rocket Chip SOC and RISC-V ecosystem.

Intuitive to software developers.

Many free tools available for IDE and testing without going to Verilog/SV simulators.

Chisel is from an agile governing body and will get you new features quickly.

Not clear: How inheritance is useful in chip design in Chisel? I mean class xyz extends pqr type inheritance. Possibly better than a module having to use parameters to customize hardware logic in SV.

SV Highlights

Unmatched RTL code base including Verilog 2001 RTL code because SV is backwards compatible with Verilog 2001.

Large set of features supporting verification and mature UVM methodology.

C/C++ code base available for extension using any of Direct Programming Interface (DPI) or Verilog Procedural Interface (VPI).

A ticket to jobs in big chip companies: SV is what is used in large semiconductor companies to verify and quite often to develop RTL. Knowing SV is a must for modern ASIC design.

Ability to model sub clock cycle delays, gate level and simple transistor level behavior.

Intuitive to electrical engineers.

Massive and overwhelming 1000+ page specification of the language => impossible to create fully compliant tool chain.

From standard governing body, that is IEEE. This means that one can be sure of the stability of the standard. You can commit to creating many designs in SV and be confident of many years of shelf life without having to worry about incompatible version changes.

Abstraction vs Accuracy

In the continuum of ability to express detail vs designer productivity, Chisel scores well on productivity and loses a bit of expressibility of low level timing. Raw SV without any additional scripting extensions is somewhat inferior to Chisel.

Chisel vs SV + VerilogMode + code generators

Chisel though attractive to developers still provides only a comparable productivity against scripting extended SV. Especially, the free tool of VerilogMode takes SV coding to an even higher abstraction level than Chisel. You could also extend the VerilogMode with additional TCL/PERL/Python scripts to get very good productivity. If you are a developer interested in participating in opensource code and the RISC-V ecosystem, Chisel is the go to HDL for you. If you are aspiring to be a RTL designer in existing medium to large semiconductor companies, SV is the go to HDL for you. Anyways, Chisel is becoming more important by the day because the power of the crowd increases quadratically with the population size.

Future

I think Chisel could very well rule the HDL space for the next 5 years. Beyond that, High Level Synthesis (HLS) and AI enabled coding frameworks could outdo both Chisel and SV.

In the HLS space, there are offerings from AMD Xilinx, Siemens EDA and free tools. In the AI enabled space there are no contenders now. But, if natural language processing AI tools are focused on the chip design process of Spec -> RTL we may see magic! or nightmare :)